Mumbai: In a groundbreaking recognition, the semiconductor industry has introduced the “Mahapatra Reliability Model,” named after Professor Souvik Mahapatra of Indian Institute of Technology Bombay’s (IIT-B) Department of Electrical Engineering.
His methodology for analysing and modelling transistor reliability is now incorporated into the Sentaurus Device Technology Computer-Aided Design (TCAD) software by Synopsys. This innovation promises to improve the reliability of semiconductor chips used in devices ranging from smartphones to aircraft.
Semiconductor chips, central to modern electronics, demand high performance and reliability over their lifecycle. With billions of nano-sized transistors packed into each chip, ensuring their long-term functionality is both complex and critical.
Mahapatra’s research over two decades has significantly advanced the industry’s understanding and control of transistor degradation mechanisms.
Mahapatra’s work involves collaborations with global industry leaders such as IBM, Intel, Micron, and Applied Materials. His contributions have enhanced the reliability of advanced Complementary metal-oxide-semiconductor (CMOS) logic and memory technologies, essential for technology development. He has devised accelerated stress tests and predictive models to evaluate transistor performance over time, mitigating risks associated with underestimating or overestimating degradation.
“The degradation of transistor performance at normal operating conditions of a chip becomes appreciable only at a very long time close to the end of product life. Since reliability must be estimated during technology development, short time accelerated stress tests are done to speed up transistor degradation, and theoretical projection methods are used to estimate its severity at the end-of-life under normal operating conditions”, said Mahapatra.
He added, “Error in the theoretical model can lead to either underestimation or overestimation of degradation during the technology development phase with significant consequences; either the release of a defective product or an unnecessary increase in the expense and time due to over-optimisation.”
Dr. Chandra Mouli of Micron lauded Mahapatra for his exceptional understanding of transistor reliability challenges, calling his collaboration “fruitful and indispensable.” IBM’s Dr. Mukesh Khare praised his advancements in logic technology scaling, while Synopsys has integrated his model into their TCAD software, acknowledging his achievements with an award at the International Electron Devices Meeting (IEDM) 2024.
